A flash memory is a non-volatile electrically erasable data storage device that evolved from electrically erasable programmable read-only memory (EEPROM). The two main types of flash memory are named after the logic gates that their storage cells resemble: NAND and NOR. NAND flash memory is commonly used in solid-state drives, which are supplanting magnetic disk drives in many applications. A NAND flash memory is commonly organized as multiple blocks, with each block organized as multiple pages. Each page comprises multiple cells. Each cell is capable of storing an electric charge. Some cells are used for storing data bits, while other cells are used for storing error-correcting code bits. A cell configured to store a single bit is known as a single-level cell (SLC). A cell configured to store two bits is known as a multi-level cell (MLC). In an MLC cell, one bit is commonly referred to as the least-significant bit (LSB), and the other as the most-significant bit (MSB). A cell configured to store three bits is known as a triple-level cell (TLC). Writing data to a flash memory is commonly referred to as “programming” the flash memory, due to the similarity to programming an EEPROM.
The electric charge stored in a cell can be detected in the form of a cell voltage. To read an SLC flash memory cell, the flash memory controller provides one or more reference voltages (also referred to as read voltages) to the flash memory device. Detection circuitry in the flash memory device will interpret the bit as a “0” if the cell voltage is greater than a read reference voltage, Vref, and will interpret the bit as a “1” if the cell voltage is less than the read reference voltage Vref. Thus, an SLC flash memory requires a single read reference voltage Vref. In contrast, an MLC flash memory requires three such reference voltages, and a TLC flash memory requires seven such reference voltages. Thus, reading data from an MLC or TLC flash memory device requires that the controller provide multiple read reference voltages having optimal values that allow the memory device to correctly detect the stored data values.
Determining or detecting stored data values using controller-provided read reference voltages is hampered by undesirable physical non-uniformity across cells of a device that are inevitably introduced by the fabrication process, as such non-uniformity results in the read reference voltages of different cells that store the same bit value being significantly different from each other. The detection is further hampered by target or optimal read reference voltages changing over time due to degradation of the flash read channel over time adverse, which may be caused by, for example, changes in temperature, interference from programming neighboring cells, numerous erase-program cycles, read disturbance effects, and data retention effects. Errors in detecting stored data values are reflected in the performance measurement known as bit error rate (BER). The use of error-correcting codes (ECCs) can improve BER to some extent, but the effectiveness of ECCs diminishes as improved fabrication processes result in smaller cell features.
An effective scheme for detecting stored data values should adapt to changes in the flash read channel in order to achieve optimal or near-optimal performance. It is known to utilize adaptive channel tracking algorithms in flash memory systems to adaptively adjust read reference voltages, re-computer reliability messages, and make other changes that improve performance based on changes in the flash read channel. For example, known adaptive channel tracking algorithms track variations in the flash read channel and maintain a set of updated channel parameters. The updated channel parameters are used, for example, to adjust hard/soft read reference voltages and to re-compute reliability messages. Typically, known adaptive channel tracking algorithms assume that the underlying write voltage distributions are Gaussian or Gaussian-like and that the success of estimating the optimal read reference voltage is dependent on the success of estimating Gaussian parameters. Such algorithms are relatively complex and computationally intensive to perform. In addition, such algorithms can result in performance penalties due to the explicit reliance on assumptions about the underlying Gaussian or Gaussian-like distributions that may not be accurate.
One known adaptive channel tracking algorithm tracks a disparity metric and adjusts the read reference voltage based on the disparity metric. Disparity can be defined as the ratio of the number of 1 bits in a bit sequence to the total number of bits in the bit sequence. The tracking algorithm causes one or more pages of flash memory to be read multiple times using different read reference voltages, which are known as soft reads, and calculates the disparity metric. The read reference voltage that results in a disparity metric of 0.5 (i.e., equal number of 1 bits and 0 bits in the sequence) is the chosen as the optimal read reference voltage. While this method is effective when the two Gaussian cell voltage distributions have nearly the same standard deviation, it can result in a poor estimate for the read reference voltage when the standard deviations differ significantly.
Accordingly, a need exists for an adaptive channel tracking algorithm that tracks changes in the flash read channel and makes appropriate adjustments to the read reference voltage based on the changes.